RTL Verification

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UVM: Monitoring/Binding DUT Internal Signals

There are three approaches related to functional verification: black-box, white-box, and gray-box. In this work, a gray-box method is proposed to know the value of internal signals to the DUT. A new class called logic analyzer is created and connected to the DUT using the same approach as the agents. The link between the RTL design and verification components is the top module, where the DUT interface (I/O ports) connects to the virtual interfaces of the agents and, in this case, the logic analyzer. 

November 14, 2024
Verification
SystemVerilog

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SOLID Principles in SystemVerilog for Verification

In this article, we will explore how to apply the SOLID principles within the context of SystemVerilog for verification purposes. Originally introduced by Robert C. Martin in the early 2000s, the SOLID principles are a set of five guidelines aimed at improving the design and maintainability of object-oriented software. The acronym SOLID was subsequently coined by Michael Feathers to represent these key principles. The five principles are:S - Single Responsibility Principle. O - Open/Closed Principle. L - Liskov Substitution Principle. I - Interface Segregation Principle. D - Dependency Inversion Principle

August 8, 2024
Verification
SystemVerilog

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Randomization with Systemverilog - Second Part

Discover how to effectively use the unique constraint and explore various methods for randomizing sequences in our comprehensive article.

August 8, 2024
Verification

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Randomization with Systemverilog

Developing a test where simulation parameters are randomized enables achieving better coverage of the DUT’s state space by simulating different test seeds. This methodology reduces the time required for test creation and maintenance. If a directed test is required, it can be created by adding constraints to the random test.

August 8, 2024
FPGA
RTL
Verification