ASIC Design

-Silicon-tested ultra low power (48.31 pJ/cycle @1MHz per core on 0.18um commercial process).
-Ultra-Compact RISC-V 32RVI compatible microcontroller: dual and single core IP solutions (less than 32k gates per core)
-Include SPI, Bootstrap, UART and SRAM memory controllers.
-Full instruction-set implementation (32RVI 32-bit base integer) with custom special GPIO instructions
-IP is capable of replacing 8 and 16-bit microcontroller solutions while being flexible and expandable to 32-bits, maintaining complete compatibility to RISC-V open-source toolchains.
-Configurable clock-gated 32-bit bus manager: Facilitates power management and integration of other IP blocks to the RISC-V core.

-Delivered entirely new micro-architecture definition and RTL code for new features in Tx/Rx interfaces including congestion control, port sub-division and virtual lane management (while maintaining compatibility to previous generation ASICs)
-Expanded legacy data crossbar to accommodate new speed and data formats with backwards compatibility
-Enhanced data throughput in legacy TX/RX ports with backwards compatibility
-RTL code developed for a new ARM-based general control manager including integration of SRAM, PVT and proprietary blocks.
-RTL interface to AlphaWave 100Gbps SERDES, including new FEC modules.
-Drove the relation with backend provider on DFT, floorplanning, place & route for both ASICs
-Synthesis verification (all blocks) including post Place & Route timing and power closure in coordination with backend provider.