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Digital FPGA & ASIC design - Clock domain crossing (CDC)
The principles of synchronous digital design state that we must have a clock, which will nicely mark the rhythm of the different signals traversing our device. We can think of this clock as a sort of orchestra director, which will make sure that everyone does its job exactly when it is required - not before, nor after.However, complex digital designs will often have more than one clock domain. When this happens, it is like having a whole new orchestra, playing side by side to the old one. If we keep them away from each other, they will both play independently, each at its own pace - but what happens when we need to make them play together? Which director will the different instruments follow? What happens when one orchestra needs to “borrow” a player from the other one in the middle of the concert? This is the problem we face when dealing with clock domain crossings, or CDCs.