Our Blog

Real-Time Systems and Concurrency: A Developer’s Guide

When it comes to embedded systems, especially in fields like industrial control or medical devices, getting your code to run efficiently, predictably, and safely is paramount. You’ve likely put in the hard work to design detailed, robust systems, but without a solid grasp of real-time concepts and concurrency, your efforts might not achieve the desired reliability. This is where understanding Real-Time Operating Systems (RTOS) like Zephyr comes into play. At Emtech, we build a lot of embedded systems, so I’d like to share and explore why real-time systems and concurrency are crucial for embedded developers and how they can help you build better, more reliable products.

Hardware In The Loop

Hardware-in-the-Loop (HIL) is a technique for the development and validation of embedded systems that verifies application behavior directly on the physical target hardware. Because increasing system complexity in sectors like automotive and aerospace makes pure simulation insufficient, HIL allows for safe testing of risky scenarios. This ensures every software change is validated under real operating conditions, guaranteeing expected interaction between hardware, drivers, and the OS.

Generating a random variable with uniformly distributed maximum over a window with configurable size

In verification, when testing a device with random inputs, it is important to ensure that the values used span the entire operational range. This is typically accomplished by using a uniform distribution for the input stimulus, often with additional weighting on boundary values to more effectively test corner cases.

TinyML in Action: Building a bird detector that fits in the palm of your hand

In recent years, artificial intelligence in microcontrollers (TinyML) has gone from being a laboratory curiosity to becoming a real tool for environmental monitoring, health, and industrial automation. This article shows how we transformed gigabytes of raw audio—the songs of six Patagonian species—into a fully INT8-quantized model that takes up just 60 kB of Flash and takes less than a second to classify a clip on an ESP32.

UVM Phases

UVM phases are virtual methods defined within the `uvm_component` class. This class can be extended to create custom components such as scoreboards, monitors, and drivers. When extending this class, only the necessary phases are implemented, it is not mandatory to implement all of them.

UVM Config Database

The `UVM_config_db` is a global database that stores key-value pairs, similar to Python dictionaries. The values can be of various types, such as integers or objects and so on. Keys consist of a hierarchical instance path and a field name: the path defines the scope where the value is visible, and the field name identifies the specific data entry.

UVM Factory

The UVM Factory is a software design pattern employed in UVM. It operates as a singleton, meaning it maintains a single class instance. This pattern enables the overriding of objects and UVM components. In essence, it allows the creation and replacement of these elements without requiring modifications to the testbench.

DPI, Python, and Wireshark Integration

In previous blogs, we have explained the fundamentals of DPI and how to connect Wireshark to a testbench to obtain real-time visualization of stimuli. In this blog, we will detail a use case (real-life scenario) where DPI will be used with Python for stimulus generation, and Wireshark will be used for traffic visualization.‍

Integrating Wireshark with UVM: A High-Level Overview

Integrating Wireshark with UVM enables real-time packet capture and analysis during network simulations. By streaming generated packets directly from UVM to Wireshark using a Python-driven pipe, users gain immediate visibility into network traffic, enhancing debugging efficiency and flexibility.

Defining Strategy with Verification and RTL Teams

Leading Cross-Disciplinary Projects at EmTech

Technology Evolution: Real Progress or Just an Illusion?

Backward Compatibility in Technology

UVM: The Gold Standard for Hardware Verification

Remote Work: The Freedom and the Cost

Innovation Begins with a Question

Challenges in FPGA and ASIC Verification

Effective Debugging with Valgrind and GDB: Insights from Nicolas Bertolo

Avoiding mistakes vs. amplifying the good

FPGAs and Tech Communities: Innovation Through Shared Learning

Knowledge management in the tech industry

2024-2025: Building a Scalable and Sustainable Business

Ship of Theseus and interfaces

Innovation at New Space: How companies that listen to their customers are leading the industry

Regulations and Software Development: How Emtech Ensures Reliability on Every Project

Formal verification vs. functional: Key differences

The Growth of EmTech's Design Verification Team: Lessons and Accomplishments of 2024

From Bahia Blanca to EmTech: The Journey that Changed My Professional Perspective

Technology and Art: Keys to Successful Entrepreneurship

Learning and Networking: Keys to Success in the Workplace

EmTech CoffeeCon 2024: How a Virtual Event Is Redefining Remote Team Collaboration?

How FPGAs Improve High Performance Computing

From Communication to Collaboration: How Client Engagement Drives Results?

External collaborations and internal growth: The formula for success in EmTech

Everything You Need to Know About Zephyr and How to Select the Best Developers

Mastering High-Speed Signals: Implementing IDELAYE3 Xilinx IP for FMC Interfaces

In modern high-speed digital systems, precise timing is critical, because signals arriving at the FPGA often exhibit jitter, a small, unintended variation in signal timing. This phenomenon can disrupt the reliability of data sampling, leading to errors in the data acquisition.Our implementation is based on the FMC-01, a FMC board connected to a Zynq UltraScale+ FPGA, developed by Emtech that enables both signal capture and generation with an 8-channel/16-bit ADC (ISLA216P25) working at 200 MSPS and a dual-channel 16-bit DAC processing at 400 MSPS.

Complete Guide: Implementing IoT in the Agricultural Sector

How Face-to-Face Meetings Transformed Our Team: EmTech's Experience in Bariloche

Proactivity culture in EmTech and rydev

The Future of Supercomputing: Innovation and Challenges in the Digital Age

LEGO: A Childhood Passion That Lasts

DPI basics - Part 1

DPI (Direct Programming Interface) in SystemVerilog enables seamless integration with C, Python, MATLAB, and more, enhancing UVM testbenches for advanced verification. Learn how import and export mechanisms work, enabling bidirectional communication with external applications. Discover how to integrate complex algorithms, external libraries, and simulation tools for a more flexible and powerful verification environment.

Vapourtec Ltd Revolutionizes Peptide Synthesis with Peptide-Builder at TIDES Europe

Methodologies and Collaboration: The Key to Success in EmTech

On interfaces and backward compatibility - Part 1 of 2

Interfaces define how systems interact, whether in hardware or software. In this blog, we explore interfaces, backward compatibility, and their impact on long-term system stability. From the Ship of Theseus to FM broadcasting, we examine real-world examples that highlight the importance of designing robust and future-proof systems.

Growing Through Connection: How December Prepares Us for Success?

ee2ee2e

Troubleshooting: Synchronizing Data Arrival to a DAC from a Zynq Ultrascale+ FPGA

Synchronize the arrival of data to a DAC from a Zynq Ultrascale+ MPSoC FPGA. The FPGA transmits data samples to a Texas Instruments DAC3283 via an LVDS interface in DDR mode, utilizing LVDS pairs for high-speed communication. LVDS is a widely used signaling standard, valued for its low power consumption, high noise immunity, and suitability for high-performance applications. This synchronization challenge is particularly interesting due to the stringent timing requirements imposed by the DDR mode and the precision required to close timing on the DAC interface at high frequencies. This article explores two options for synchronizing the interface: applying delays to data signals and adjusting the phase between data and clock.

Virtual sequences and virtual sequencers: Part 2

In modern verification environments, UVM sequences serve as the backbone of stimulus generation. This comprehensive guide is divided into two parts, taking you from fundamental concepts to advanced implementation techniques. This is part two.

Virtual sequences and virtual sequencers

In modern verification environments, UVM sequences serve as the backbone of stimulus generation. This comprehensive guide is divided into two parts, taking you from fundamental concepts to advanced implementation techniques.

UVM: Monitoring/Binding DUT Internal Signals

There are three approaches related to functional verification: black-box, white-box, and gray-box. In this work, a gray-box method is proposed to know the value of internal signals to the DUT. A new class called logic analyzer is created and connected to the DUT using the same approach as the agents. The link between the RTL design and verification components is the top module, where the DUT interface (I/O ports) connects to the virtual interfaces of the agents and, in this case, the logic analyzer. 

From LoRa to LoRaWAN: How Zephyr OS Empowered Emtech's IoT Evolution

In the rapidly changing IoT/AgTech field, Emtech strives to deliver innovative solutions for agriculture. We upgraded from LoRa to LoRaWAN gateways to enable bidirectional communication with our nodes. This led us to adopt Zephyr OS, offering a more robust development experience for LoRaWAN.

SOLID Principles in SystemVerilog for Verification

In this article, we will explore how to apply the SOLID principles within the context of SystemVerilog for verification purposes. Originally introduced by Robert C. Martin in the early 2000s, the SOLID principles are a set of five guidelines aimed at improving the design and maintainability of object-oriented software. The acronym SOLID was subsequently coined by Michael Feathers to represent these key principles. The five principles are:S - Single Responsibility Principle. O - Open/Closed Principle. L - Liskov Substitution Principle. I - Interface Segregation Principle. D - Dependency Inversion Principle

Working with Xilinx's AXI Quad SPI in Linux? Streamline Your Setup with This Simple Fix

Last week, our dev team was knee-deep in a project integrating Xilinx's AXI Quad SPI IP into a Petalinux system. Everything seemed to be in order, but they kept hitting a wall when trying to configure the SPI device. After hours of troubleshooting, and a few dips into linux kernel driver debug features (more on this on future posts!), they finally stumbled upon a simple solution that saved the day!

Dashboard Creation with Python, Pandas, and Dash

Interactive dashboards are an essential tool for visualizing and exploring data. With Python libraries like Pandas and Dash, creating these dashboards becomes straightforward and efficient. During this post, we'll walk you through the process of building a dashboard step by step, from loading and preprocessing the data to creating interactive plots and generating a web-based interface.

Zephyr OS, A brief introduction

The Zephyr Project emerged on the embedded systems scene in 2016 as a new real-time operating system (RTOS) for embedded and IoT devices. It's a collaborative effort led by the Linux Foundation, along with Wind River, Synopsys, and NXP. Their goal was to create a multi-platform RTOS that leverages proven concepts from the Linux operating system, such as kconfig, device trees, and the driver model.‍

Randomization with Systemverilog - Second Part

Discover how to effectively use the unique constraint and explore various methods for randomizing sequences in our comprehensive article.

Qt Development: Challenges and Strategies for Efficient Code Inheritance

Developing software based on preexisting code is an art in itself. When this challenge is combined with the use of the Qt framework and an inefficient legacy architecture, the complexity and opportunities multiply. In this blog, we will explore not only the benefits and challenges of inheriting code in the world of Qt but also how to address an inefficient legacy architecture and face the eternal dilemma of investing time in redesign versus saving time by maintaining the existing architecture.

How can Raspberry Pi's potential be unleashed in developing HMI applications for IoT with intensive loads?

Unlocking the Raspberry Pi's full potential for developing HMI applications for IoT involves a symphony of components, from the nimble Buildroot OS to the versatile OPC UA Server, TCP/IP Server, Serial Interface, RDP, SFTP, Camera, and seamless OS updates. Each element plays a pivotal role in enabling efficient communication, remote access, and adaptability, making it an ideal solution for the challenges of demanding industrial scenarios.

Digital FPGA & ASIC design - Clock domain crossing (CDC)

The principles of synchronous digital design state that we must have a clock, which will nicely mark the rhythm of the different signals traversing our device. We can think of this clock as a sort of orchestra director, which will make sure that everyone does its job exactly when it is required - not before, nor after.However, complex digital designs will often have more than one clock domain. When this happens, it is like having a whole new orchestra, playing side by side to the old one. If we keep them away from each other, they will both play independently, each at its own pace - but what happens when we need to make them play together? Which director will the different instruments follow? What happens when one orchestra needs to “borrow” a player from the other one in the middle of the concert? This is the problem we face when dealing with clock domain crossings, or CDCs.

Relevance of PCB Design in the Current Industry

In an increasingly interconnected world, where electronics span from mobile devices to autonomous vehicles, communication systems and high-precision medical systems, PCB design stands as a crucial foundation for innovation. It provides the physical and electrical structure that enables devices to function correctly and communicate efficiently with each other.

Randomization with Systemverilog

Developing a test where simulation parameters are randomized enables achieving better coverage of the DUT’s state space by simulating different test seeds. This methodology reduces the time required for test creation and maintenance. If a directed test is required, it can be created by adding constraints to the random test.

Linux for Embedded Devices - Third Approach

In the previous article, we looked at how hardware starts, found the bootloader, loaded the kernel, searched and configured the drivers and started the user space .In this article we must deepen in the user space initialization process.

Management of complex projects

Today, more than an article, we are giving you a presentation that was made internally to give a small overview of some tools, frameworks and strategies that can help us lead projects or better understand the processes that must be done to successfully meet the projects with the objectives. that we work every day. It is important to gain a deeper understanding of project planning and execution, which is accompanied by challenges and setbacks. When leading complex projects, different types of complexities can arise, from their structure and scope to their changing nature, along with power and political dynamics within the project team and external stakeholders. I hope you like it and can learn a little more about project management.

Integrate an OPC UA Server into an embedded or PC application using the QT platform

In today's post we will introduce you to automating industrial or Internet of Things equipment through an API developed with the OPC UA standard using QT as a development platform. QT allows you to create cross-platform applications, so you could create an application that runs both on a PC and on an embedded system like a raspberry pi.

Linux for Embedded Devices - Second Approach

In the previous article, we saw what Linux is, what it is suitable for, and what is the basic structure from a kernel view. In the present article we discussed, deeper, what is the structure of that called userland.

Linux for Embedded Devices - First Approach -

Linux is a very popular operating system in many computer systems and it's a first choice on data centers and high end software infrastructure, but the flexibility of the penguin’s kernel made this to be very suitable for extremely low end devices. Come with me and discover the blessings and curses of the linux kernel in embedded systems, low resource devices and (not-so-)hard-real-time things.