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UVM: Monitoring/Binding DUT Internal Signals
There are three approaches related to functional verification: black-box, white-box, and gray-box. In this work, a gray-box method is proposed to know the value of internal signals to the DUT. A new class called logic analyzer is created and connected to the DUT using the same approach as the agents. The link between the RTL design and verification components is the top module, where the DUT interface (I/O ports) connects to the virtual interfaces of the agents and, in this case, the logic analyzer.