ASIC CAPABILITIES
P. LANGUAGES
- VHDL
- System Verilog
- Verilog
- HLS
- Scripting (TCL, Python,...)
- C/C++
- High Level Languages
- Matlab
- UVM
- OVM
SPECIFICATION
Algorithms & Modelling
rTL
Physical Layout
Verification
Implementation & Testing
An ineffective verification strategy can consume valuable time and resources. Therefore, it is crucial to depend on expertise and experience. With over 15 years of experience and a profound understanding of the verification discipline, we recognize that the cornerstone of successful ASIC design and development is the careful selection of effective verification criteria.
Our verification engineers have mastered several ASIC verification strategies and guidelines that allow customers rapid and reliable closure of the verification effort for the most complex ASICs.
Two ASIC designs of more than 100 million gates each, on a 7 nm TSMC process.
-Migration of legacy UVM/OVM environments to new environments
-Generation and implementation of the pre-silicon test plan (blocks and full-chip), including execution and management (Jira and GitHub)
-Cadence’s VIPs integration for an AlphaWave PCIe controller (5Gen), I2C and SPI-IP interfaces, into the verification flow for both ASICs.
-System integration and verification of a Tensilica microcontroller IP including integration of SRAM.
-Platform-level validation of the controller (using new firmware).
System implementation of algorithms and signal processing techniques to generate SAR RADAR data, simulating the transmitted and received signals as obtained from a real SAR antenna.
FPGA implementation includes: beam-forming, polarization, bandwidth, and beam steering.
Satellite Communication
Satellite Platform
High Performance Computing
Industrial Instrumentation & Control
Telemetry
Cloud Systems
Video Streaming
Radar
Sensor Adquisition & Procesing
Communications
IOT
Mobile
Test Systems